Efficient Implementation of Reconfigurable MIMO Decoder Architecture

Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) are two dominant technologies in emerging wireless communication. MIMO transmission increases the capacity and reliability o a wireless system without increasing its bandwidth. OFDM divides a wideband channel into multiple narrowband subchannels via a computationally efficient fast fourier transform (FFT) operation, but it requires identical baseband processing for each of the subchannel. Combining OFDM with MIMO technique increase spectral efficiency, throughput and improves the link reliability. The MIMO decoder is one of the most complex blocks in MIMO transceiver. MIMO decoding is essentially an inversion of a complex matrix channel and it can be achieved by using a variety of MIMO decoding algorithms. The choice of algorithm and antenna configuration depends on the available resources, channel conditions, power budget and throughput requirement. The existing MIMO decoder design needs to be upgraded in order to allow new MIMO decoding algorithm and wireless communication standards. This necessitates the need for a programmable accelerator block to implement the MIMO decoder. This thesis proposes an area efficient implementation of a programmable MIMO decoder accelerator that targets MIMO decoding tasks of OFDM system.