HYBRID DESIGN, MODELLING, AND SIMULATION OF A 4-BIT BINARY MULTIPLIER USING VIVADO, SIMULINK, AND KINTEX-7 FPGA

The design of binary multipliers is a critical aspect of any reliable hardware in computing and computer engineering. In this paper, the design of a 4 bit binary multiplier has been undertaken, starting with a review of the importance of binary multipliers and wide areas of application. The paper then presents the multiplication methodology which involves an accumulator, a full adder, and a control circuit. The accumulator and full adder were designed using VHDL in the Vivado IDE, whereas the control circuit was modelled using the powerful technique of State flow in Simulink. The 4 bit binary multiplier is then modelled and simulated using the combination of Simulink and VHDL. Results obtained from the simulation verified the accuracy of the design methodology.