Analysis Parameter of Vedic Multiplier using different Logic Gate

Abstract? With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well-known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we have developed three designs for Urdhwa Multiplier. In first design we have developed 4:2 compressors based on full adder and utilization in term of 42 delays and 21 areas. In second design we have developed 4:2 compressors based on XOR gate and utilization in term of 36 delays and 24 areas. In third design we have developed 4:2 compressors based on full adder and utilization in term of 28 delays and 18 areas. This all design and experiments were carried out on a Xilinx Vertex-7 series of FPGA and the timing and area of the design, on the same have been calculated.