Implementation of High Speed Low Power 16 Bit BCD Multiplier Using Excess-3 Codes

The paper mainly concentrates on the development of the new architecture for BCD parallel multiplier that exploits some properties of two different redundant BCD codes to speed up its computation: the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In this we have developed a 16 bit BCD multiplier using some new techniques to reduce significantly the latency and area of previous representative high-performance implementations. The key role plays by the Partial product generation in parallel using a signed-digit radix-10 recoding of the BCD multiplier with the digit set [-5, 5], and a set of positive multiplicand multiples (1X, 2X, 3X, 4X, 5X) coded in XS-3.By using the above approach of encoding there are several advantages like mainly it is a self-complementing code, so that a negative multiplicand multiple can be obtained by just inverting the bits of the corresponding positive one. Also, the available redundancy allows a fast and simple generation of multiplicand multiples in a carry-free way and finally, the partial products can be recoded to the ODDS representation by just adding a constant factor into the partial product reduction tree. Since the ODDS uses a similar 4-bit binary encoding as non-redundant BCD, conventional binary VLSI circuit techniques. We had developed a new approach of BCD addition for the final stage. The above developed architecture of 4X4 has been synthesized a RTL model and given better performance compared to old version multipliers