Low Power Nine-bit Sigma-Delta ADC Design Using TSMC 0.18micron Technology

In Sigma-Delta analog to digital conversion method, the input signal is represented by a sinusoidal signal of magnitude 1V at a signal band of 1MHz.The modulator is operated with ±1.8V supply voltage and a fixed oversampling ratio of 128. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 32. It achieves a resolution of 9-bits by occupying silicon chip area of 8043μm2 and by consuming a total power of 540.48nW. A first order sigma-delta modulator, which is implemented using TSMC 180nm technology using Mentor Graphics Pyxis tool and the second order CIC decimation filter is implemented in Verilog HDL.