RTL DESIGN OF EFFICIENT MODIFIED RUN-LENGTH ENCODING ARCHITECTURES USING VERILOG HDL

Compression is an efficient technique to reduce the memory size and to improve the speed. In ECG signal compression, modified run-length encoding plays a significant role to compress the digitized ECG signals. The main objective of this paper is to realize an efficient architecture for modified run-length encoding compression and decompression algorithms. The proposed architectures designed in verilog HDL. And the designed verilog HDL modules are simulated and synthesized using Xilinx ISE 13.1 for RTL design.