Review Paper on Area Efficient Vedic Multiplier using Barrel Shifter
Journal: International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) (Vol.6, No. 1)Publication Date: 2017-03-11
Authors : Pankaj Prajapati; Neetesh Raghuwanshi; Anurag Rishishwar;
Page : 124-127
Keywords : Vedic Multiplier; Compressor; Xilinx Simulation;
Abstract
Abstract: Multiplication is an important function in arithmetic operations. A CPU (central processing unit) devotes a considerable amount of processing time in performing arithmetic operations. Multiplication requires substantially more hard-ware resources and processing time than addition and sub-traction. Digital signal processors (DSPs) are the technology that is omnipresent in engineering Discipline. Fast multiplication is very important in DSPs for digital filter, convolution, Fourier transforms etc. In this proposed research work an attempt will make for making a novel multiplier using Nikhilam Sutra and Barrel Shifter. The proposed multiplier will have not only fast response but also having less number of component, area and power consumption.
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Last modified: 2017-03-12 00:33:33