Performance Analysis of Proposed Full Adder Cell at Submicron Technologies

This paper presents an analysis of high-speed and low-voltage full adder circuit analysis. The proposed circuit analyzed for parameters like logic levels and power consumption. Full adder is an important circuit for designing many types of processors like microprocessors, digital signal processors, image processing and various VLSI applications etc. Many blocks of the designs, adders lie in critical data path of the circuit which affects the overall performance of the system. In this regards this paper analyses the proposed full adder cell at block level. Ripple carry adder is taken as the benchmark circuit to analyze the proposed full adder cell at 45nm technology. KEYWORDS: Full