A SURVEY ON A HIGH SPEED BINARY FLOATING POIN T MULTIPLIER USING DADDA ALGORITHM IN FPGA

In Digital Signal Processing, Floating Point (FP) Multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. Most of the DSP applications need floating p oint numbers multiplication. The possible ways is to represent real numbers in binary floating point numbers format. The IEEE 754 standard represents two floating point formats, Binary interchange format and Decimal interchange format resp. The main object of this paper is to reduce the power consumption and to increase the speed of execution for multiplying two floating point number using FPGA.