Optimized FIR Filter using Distributed Arithmetic Architecture

FIR filters are digital filters with impulse response of finite duration, because it settles to zero in finite time. They are also known as non-recursive filter because they do not have the feedback part. FIR filters can be used to design almost any type of frequency response in digital form and can be implemented using adders, multipliers and delay elements. Various architectures can be used for implementing FIR filters, one such is the Distributed Arithmetic. This is a multiplier less architecture, since multipliers are the speed limiting elements in a VLSI circuit. Thus it consumes less area than normal FIR filter by replacing multipliers with shift and add operation. In this paper an FIR filter is designed using Distributed Arithmetic in Xilinx ISE 14.7 by programming in VHDL.