Low Power Single Phase Clock Multiband Flexible Divider using Low Power Techniques

In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18μm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow(S) counter and operates in 2.4 to 5 GHz resolution selectable from 1 to 25 MHz However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Low power Techniques like Sleep Transistor Approach.