Study of Architectural Design of VLSI

The paper presents an overview on architectures for design implementations of VLSI architecture schemes as specified By standardization committees of the ITU and ISO. Implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures will be evaluated. It is also dedicated decoder chips are included. Architectures are presented for reported design examples from the literature. Heterogeneous processors outperform homogeneous processors because of adaptation to the requirements of special subtasks by dedicated modules. Majority of heterogeneous process incorporate dedicated modules for high performance subtasks of high regularity By normalization to a fictive 1.0 pm CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural style. This relationship indicating a figure of merit for silicon efficiency.