Design, Comparison and Implementation of Multipliers on FPGA

In this paper comparison of array, booth radix-2 and booth radix-4 multipliers have been presented. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. In this paper we determine the best solution to this problem by comparing a few multipliers. The proposed architectures are synthesized using Xilinx tool and implemented on FPGA. Based on the theoretical and experimental estimation, analysis was carried on results such as the amount of hardware resources and delay. Proposed multipliers can be used for high performance applications like signal processing, image processing.