Implementation of low power CMOS design using Adiabatic Improved Efficient Charge Recovery Logic

This paper presents a new adiabatic circuit technique called Positive Feedback Adiabatic Logic (PFAL). Power reduction is achieved by recovering the energy in the recovery phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. The main objective of this paper is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. The adiabatic logic structure dramatically reduces the power dissipation. The adiabatic switching technique can achieve very low power dissipation, but at the expense of circuit complexity. Adiabatic logic offers a way to reuse the energy stored in the load capacitors rather than the traditional way of discharging the load capacitors to the ground and wasting this energy.