Low Power Optimization Of Full Adder 4-Bit Adder And 4-Bit BCD Adder

Abstract Micro-electronic devices are playing a very prominent role in electronic equipments which are used in daily life. For electronic equipment battery life is important. So in order to reduce the power consumption we implement a Sleepy technique to the electronic circuits. Sleepy technique is also called as power gating technique. In the power gating structure a circuit operates in two different modes. In the sleep mode the sleep transistors are turned OFF to reduce the leakage power. In the active mode the sleep transistors are turned ON and can be treated as the functional redundant resistances as circuit is in operation mode the power leakage should not be more than the basic full adder. When a sleepy transistor is placed at VDD it is called as the Header switch and while it is placed near the ground it is called as Footer switch. Now in our project we implement this technique to the Full-adder and then it is used in 4-Bit Adder and 4-bit BCD Adder using 90nm scale technology. Without losing the CMOS logic a new full adder is designed by reducing the number of transistors which also leads to the reduction of chip size. In almost all electronic equipment full adder is used. So this project has been done with the aim of reducing the power consumption in the full adder circuit and implementing it in 4-Bit Adder and 4-Bit BCD Adder.