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On Chip Calibration For A 7 Bit Comparator Based Asyncronous Binary Search CABS AD Converter

Journal: International Journal of Scientific & Technology Research (Vol.2, No. 11)

Publication Date:

Authors : ; ;

Page : 10-18

Keywords : Index Terms 2-step 8-bit ADC Architecture; Calibration of 7-bit CABS ADC; 7-bit CABS stage;

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Abstract An on-chip calibration technique has been proposed for a 7-bit Comparator Based Asynchronous Binary Search CABS AD Converter. The proposed design is veri-fied using an 8-bit 3.3V 10 MSs Asynchronous SAR AD Converter by integrating the calibration scheme into the AD Converter. The 8-bit Asynchronous SAR AD Converter consists of a track-and-hold followed by a two-step conversion process. The two-step architecture consists of a 1-bit course and a 7-bit fine converter. The 1-bit coarse converter is implemented using the SAR-CC principle and the 7-bit fine converter is implemented using the CABS principle. The 7-bit CABS sub-AD converter consists of 127 comparators with differ-ent threshold voltages. All these 127 comparators with different threshold voltages are calibrated using a calibration technique in which the thresholds are adjusted to the desired value by tuning the total current flowing through the differential pair in the comparator circuit. The calibration technique and the AD converter have been designed in 0.18 mm CMOS technology with a supply voltage of 3.3 V. The simulation results showed an ENOB of 6.7 for SNDR of 42.09 dB at Nyquist frequency.

Last modified: 2014-03-17 17:42:18