MPEG-4 PART 10/HEVC DCT ARCHITECTURE EFFICIENT INTEGER

In this project we have proposed a low-cost high throughput multistandard transform (MST) core, which can support MPEG 1/2/4 (8 × 8), H.264 (8 × 8 &4 × 4), and Video Codecs VC-1 (8 × 8, 8 × 4, 4×8 & 4×4) transforms. Common sharing distributed arithmetic (CSDA) algorithm combines factor sharing and distributed arithmetic sharing techniques, to exploit the available resources on FPGAs, which incorporates pipelining and parallel processing of the input samples. With the help of this architecture the throughput of the design is increased. The main strategy is to reduce the nonzero elements using CSDA algorithm. The reduction in adders in the proposed MST is achieved up to 44.5%, compared with the direct implementation method. The proposed MST core has an eightfold operation frequency throughput rate with eight parallel computation paths