DESIGN OF MULTIPLE CONSTANT MULTIPLICATION ALGORITHM FOR FIR FILTER?

Design of low power systems has become a significant performance goal in the present world. A fast and energy-efficient multiplier is required in electronics industry especially in Digital Signal Processing, image processing and arithmetic units in microprocessors.Multiplier is an important element which contributes substantially to the total power consumption of the system. In VLSI design, the designers have more constraints which include less silicon area, high speed and minimal power consumption. The Aim of this research is to design a low cost finite impulse response filter using the concept of faithfully rounded truncated multipliers. The optimization of bit width and the hardware resources are done with good accuracy. In direct FIR filter the multiple constant multiplication are implemented using the improved version of truncated multipliers.