Design of CMOS Based PLC Receiver

This paper presents a power line communications (PLC) receiver in ICs. The PLC is one in which the power pins and the power distribution networks of ICs are used for data communication as well as power delivery. PLC is used in order to reduce the number of input pins that an IC needs to couple the test data signals to each and every node. The main design objective of the proposed Low Voltage CMOS Schmitt trigger for PLC receiver is the power efficient operation, since power is one of the most important criterions in the VLSI design. Schmitt trigger circuits are widely used for waveform shaping under noisy conditions in electronic circuits. The hysteresis in a Schmitt trigger offers better noise margin and noise stable operation. In this paper, we report novel Schmitt trigger circuit designs in CMOS for operation at 1V and below using a dynamic body-bias method. The PLC receiver designed in 0.18μm CMOS technology under a supply voltage of 1V with the help of Tanner EDA tool, to achieve extreme low power consumption. It is found that the power consumption of this new PLC receiver is only 0.769mW, which is very less than presently existing designs.