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Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.6, No. 11)

Publication Date:

Authors : ; ;

Page : 524-529

Keywords : CMOS Logic; Low power; Speed; SRAM and VLSI.;

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Power leakage in a RAM cell is a major concern in today's development of shrinking size and high standby memories. To solve the power leakage problem, many researchers have proposed different ideas from the device level to the architectural level and above. SRAM designs has become the issue of significant research to increase require for laptops, integrated circuit (IC) memory cards, notebooks and hand held communication devices. The work presented here has 6T and 8T SRAM cells, that were designed in S-edit and the simulation is performed using T-spice. The model design of a 6T SRAM cell is traced from the base literature. T-Spice simulation gives the required output by measuring the average power consumed of the MOSFETs along with propagation delay. The simulation is performed using 16nm Technology. The successful operation of the designed cell is verified visually by observing the output waveforms with respect to the input waveforms in Wedit. Upon measuring and performing calculations, it is found that the EDP of 6T Cell in literature was 1.87 × 1020 Ws2 and as per simulation EDP was 1.26 × 1020 Ws2 . This shows that there is nearly 32.6% increase in power saving upon performing the simulation. Moreover a successful design of 8T SRAM cell is also modeled and the EDP is calculated to be 0.81 × 10-20 against 6T SRAM Cell. This has been achieved by introducing an inverter between BL and BLB

Last modified: 2017-11-27 19:17:11