IMPLEMENTATION OF AREA AND SPEED EFFICIENT TPFT BASED CHANNELIZATION FOR SDR APPLICATION

Channelization is the task of channel selection in a communications receiver. Usually it comprises down-conversion of the signal to base-band and channel filtering. To be able to influence the characteristics of channelization by means of software it is advantageous to realize as much as possible of the channelization functionality with digital signal processing. In base-stations several channels have to be received in parallel. An obvious approach to meet this task is to have a separate channelizer for each channel, which can be achieved through Tunable Pipelined Frequency Transform (TPFT) based channelization technique. It consists of TPFT based Filter banks and Inter leavers, which in turn a TPFT Filter bank consists of two Processing elements(PE's). This Processing elements consists of three blocks namely in commutator, Transposed Half-Band Filters and Out commutator. Transposed HalfBand Filters consists of adders which are the important part of the digital signal processing applications and also widely used in digital integrated circuits. In this paper, an attempt was made to reduce area and delay by using various adders to the existing system. Implementation of Area and Speed Efficient TPFT Based Channelization using Ripple Carry Adder (RCA), Carry Look-Ahead Adder (CLA) and Parallel Asynchronous Self-Timed Adder (PASTA) was synthesised and simulated using Xilinx ISE 14.5 tool for vertex family device and simulation results as well as synthesis report are presented in this work.