DESIGN AND IMPLEMENTATION OF ADDER ARCHITECTURES AND ANALYSIS OF PERFORMANCE METRICS

Adders are one of the most widely used digital circuits in integrated circuit design. With the advances in technology, researchers are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper the implementation of an ancient Vedic adder for 32bit size is proposed. The Vedic adder (VA) shows the improved speed performance with less time delay. The existing adders such as Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA), Carry Select Adder (CSA) and Carry Skip Adder (CKA) are implemented for 32 bit size. Adders are coded in Verilog HDL with XILNX software 14.3 on Spartan 3 kit using Chip Scope Pro analyzer. Further the performance metrics of adders such as area and delay are determined and compared.