Design and Verification of ASIP- Dual Modified Key Generator Based Encryption for Cloud Storage

Paper work proposed a new 2^n+1 modulo multiplier for dual key IDEA encryption in the design which generates less number of partial products (≤ n 2) and the less area at very high speed. The multiplication is based on Wallace tree along with specialized shifting. Coding with different combinations of eight rounds is been done at gate level i.e. fully dataflow modeling style for high throughput.. New modulo multiplication is been proposed in which multiple patterns can be done with less area. The string matching module is coded and functionally verified using VHDL language targeting Virtex IV pro FPGA and performance measures in terms of speed and resource utilization. Our work is mainly based on designing an efficient architecture (IP) for a cryptographic module for secure data trafficking and a network intrusion detection system for a high speed network. The complete designs are coded using VHDL language and are verified using Xilinx-ISE simulator for verifying their functionality.