DESIGN OF PARALLEL PIPELINED FEED FORWARD ARCHITECTURE FOR ZERO FREQUENCY & MINIMUM COMPUTATION (ZMC) ALGORITHM OF FFT

A new parallel pipelined feed forward architecture for real-time signal is proposed. A hardware oriented radix-2 algorithm is derived by integrating a twiddle factor decomposition technique in the divide and conquer approach. The butterfly structure of radix-2 algorithm is modified in accordance with the flow of signal. The new butterfly structures are designed to handle the hybrid data path which consists of real & complex data paths. The proposed approach which can be extended to all radix-2k based DITFFT & DIFFFT algorithms. The zero frequency is computed without processing the zero input data. The symmetry property is applicable to minimize the stage computation in half of the actual stage. The proposed radix-2k feed forward architectures need to use fewer hardware resources in hardware architecture. The proposed radix 2k architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix-22 architecture requires 4(log16N-1) complex multipliers, log2N real adders and N-1 complex delay elements.