HIGH-SPEED VLSI IMPLEMENTATION SYSTEMATIC SCHEME FOR DWT

The wavelet transform has proved to be the efficient transform for the decade for realtime signal processing. The scalar wavelets have been widely used in applications like signal denoising image compression and in medical fields. Wavelet transform possesses a number of desirable properties such as compact support, regularities, orthogonality and symmetry. Information or data are carried by signals in the field of communication. While transmission interference combine with the pure signal to form noise. Even though many algorithms are developed for the removal of noise in the receiver side, the SNR ratio is not appreciable to receive the original signal from the noise. Due to certain disadvantages in Fourier transform, the researchers concentrated on Wavelet transform by which removal of noise was found easy. In such case wavelet transform has to be implemented as circuit and made available in the receiver side. Thus recent researches aim in forming VLSI architecture, for wavelet transform. If wavelet transform is implemented in VLSI, the speed can be increased and thus latency, area, power can be reduced. The first architecture for wavelet transform was named as folded architecture by Parhi [10]. But the architecture found many disadvantage in terms of speed. Several other architectures were formed to increase the speed and to reduced the power. This research proposal with this literature survey aims in the VLSI architecture of wavelet transform by modifying the existing architecture. Since multipliers are available in the architecture of wavelet transform, the proposal decreses the no of multipliers there by decreasing the area. If area is reduced speed is increased.