CLOCK GATED ROUND ROBIN ARBITER FOR NOC ROUTER

Network on chip is now a day the choice of a processor designer for transfer of data in a packet based communication system as conventional bus based communication medium is not scalable with the increasing numbers of cores. In an NoC system, each core is connected to a local router and all the routers are connected via communication links. The routers as well as the communication links consume a significant amount of power which is a major concern in an NoC based system. This has led to the work that has been proposed in this paper. In this paper, we propose a low power NoC router based on the principle of clock gating technique by modifying the arbiter block of the router and compare the result with conventional Round-Robin arbiter. Here, the concept of clock-gating has been used to modify the router which has led to the reduction of dynamic power.