FPGA PROTOTYPING OF UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) WITH LOW POWER TPG BASED BIST ARCHITECTURE?

A digital system is tested and diagnosed during its lifetime on numerous occasions. Test and diagnosis must be quick and have very high fault coverage. One way to ensure this is to specify test as one of the system functions, so it becomes self-test. With properly designed BIST, the cost of added test hardware will be more than balanced by the benefits in terms of reliability and reduced maintenance cost. This paper presents a low power test pattern generator for BIST without affecting the fault coverage. The proposed test pattern generator reduces the switching activity among the test patterns. This BIST scheme is evaluated with Universal Asynchronous Receiver and Transmitter (UART) as Circuit under Test. The 8-bit UART with status register and low power TPG based BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and ISim version 14.6 and realized on Spartan 3E FPGA.