Leakage Power Minimization in ST-SRAM Cell Using Adaptive Reverse Body Bias Technique

Nowadays, we all are using battery operated devices and the devices require extremely low power to maximize the lifetime of the battery. Maximum devices are storing their data in memory. With downscaling of CMOS process, low power operation is the main area of importance in memory design. Power reduction can be achieved by many techniques. Here, in this paper, the main focus and analysis is Schmitt Trigger based SRAM (ST-SRAM) cell and use of adaptive reverse body bias technique to minimize leakage power. The total circuit simulation has been done using 180nm Technology in Cadence. Static Noise Margin is calculated here to check the read stability of the circuit. The adaptive reverse body bias technique used here increases the threshold voltage and reduces the leakage power.