Design of Full Adder in 180nm Technology Using TG and Adiabatic Logic

The main goal of this paper to produce new low power solutions for very large scale integration(VLSI).The main focus of this research on the power consumption, which is showing an ever-increasing growth with scaling down of the technologies. The full adder is the most important component of any digital system applications. To limit the power dissipation, this full adder is designed with adiabatic technique PFAL and it compare with partial adiabatic technique ECRL. These analysis have done on TANNER simulator V 7 technology. The power is reduced up to 70- 80% as compared to other methods.