Design of Area, Power and Delay Efficient High-Speed Multipliers

Multiplication is the most time consuming process in various signal processing operations like convolution, circular convolution, auto-correlation and cross-correlation. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. However area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best trade off solution among the both of them. To have features like high speed and low power consumption multipliers several algorithms have been introduced .In this paper, we describes Multipliers by using various algorithm in VLSI technology. The Wallace Tree Multipliers are compared with existing multipliers in terms of improvement in features like area, delay and power consumption by using different logical operation.