Analysis of CMOS Based Full Adders for Mobile Communications

As technology scales into the nanometer regime leakage power and noise immunity are becoming important metric of comparable importance to active power, delay and area for the analysis and design of complex arithmetic and logic circuits. In this project, low leakage 1 -bit full adder cells are proposed for mobile applications. For the most recent CMOS feature sizes (e.g., 180nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. The main goal is to reduce leakage power. Therefore a new transistor resizing approach is used for 1-bit Full Adder cells. The simulation results depicts that the proposed design also leads to efficient 1-bit full adder cells in terms of standby leakage power. In order to verify the leakage power, various designs of full adder circuits are simulated using DSCH, Micro wind and Virtuoso (Cadence).