REDUCING DYNAMIC POWER BY PULSED LATCH AND MULTIPLE PULSE GENERATOR IN CLOCKTREE?

Nowadays power consumption is an important issue in high-performance digital circuits. Reducing Nowadays power consumption is an important issue in high-performance digital circuits. Reducing the size of a clock tree is an effective approach to reduce dynamic power dissipation in digital circuit designs. Existing methods are based on reduction of the flip-flop power alone, which gives limited amount of power savings. To achieve the considerable power saving, this project gives an analysis of the pulsed- latch utilization in a clock tree. A novel approach is proposed to efficiently construct a clock tree with both pulsed-latches and flip-flop. To avoid maximum power consumption in clock tree multiple pulse generators has been proposed. An algorithm has been developed for clock tree partition based on Voronoi diagram to avoid clustering. The method is based on minimum-cost, maximum-flow formulation to globally determine the tree topology, which maintains load balance and considers the wire length between pulse generators and pulsed latches. Experimental results indicate that the proposed novel approach can reduce the power consumption by a certain extent. It is an average compared with the most recent paper on the industrial circuits and ISCAS-2012 benchmarks respectively. This method simulated in Xilinx and Modelsim software.