DESIGN AND ANALYSIS OF SRAM ARRAY STRUCTURES?

Static Random Access Memory (SRAM) is an indispensable part of most modern VLSI Designs, because of its lower power consumption, high speed and its dominates silicon area in many applications. SRAM plays a significant role in energy consumption due to the high density for evermore increased computing power in many ultra-low power applications. A novel low power 6T SRAM cell with single bitline to enhance the stability. SRAM energy efficiencies can be achieved with a wider SRAM array structure with fewer rows than columns particularly at low supply voltage. In the proposed 6T SRAM cell write operation done by charging or discharging single bit line (BL) ,which results in reduction of dynamic power consumption. Simulation results show a better efficiency for the same SRAM bit density and the same supply voltage.