HUFFMAN ENCODER AND DECODER USING VERILOG

Abstract : A binary Huffman encoder has been made using Verilog HDL on tool Xilinx ise14.6 isim simulator. The Huffman encoder has been designed and synthesized using a finite state machine. It basically reduces the repeated messages and thus contracts the message. So now the repeated messages will be send only one time. Keywords: Compression, bandwidth, lossless, lossy.