High Performance and Power Efficient Comparator Using Scalable Parallel Prefix Tree.

A new comparator design featuring of wide-range and high-speed using only digital CMOS cellsThe comparator exploits a novel scalable parallel prefix tree structure that allows the comparison outcome of most significant bit, towards least significant bit when compared bits compared bits are equal .The comparator exploits a novel scalable parallel prefix tree structure that allows the comparison outcome of most significant bit, towards least significant bit when compared bits compared bits are equal .A new comparator design featuring of wide-range and high-speed using only digital CMOS cellsThe comparator exploits a novel scalable parallel prefix tree structure that allows the comparison outcome of most significant bit, towards least significant bit when compared bits compared bits are equal .The comparator exploits a novel scalable parallel prefix tree structure that allows the comparison outcome of most significant bit, towards least significant bit when compared bits compared bits are equal .