Design of Low Power and High Speed Full Adder Cell Using New 3TXNOR Gate

In the current age of technology advancement it is necessary to design different new concepts to reduce area of the cell as well as power consumption. The adders are always meant to be the most fundamental requirements for process of high performance and other multi core devices. In present work a new XNOR gate using three transistors has been designed, which shows power dissipation of 0.03866W in 90nm technology with supply voltage of 1.2V. A single bit full adder using eight transistors has been designed using proposed XNOR cell and a multiplexer, which shows power dissipation of 0.07736W. It is implemented by using synopsys tool(version-L-2016.06-8) using custom compiler with 90nm technology.