An Efficient Design and Verification of I2C Master Core

In the current age of technology advancement is necessary to design any circuits. Before completing any tape out process in industry design, testing, fabrication and packaging are the most important steps to be considered. If the conditions are not met, then it cause a functional failure or huge loss for the company. So verification plays an important role. In conventional papers they used C, VHDL, Verilog and SystemVerilog for designing I2C master. Here also we used Verilog and SystemVerilog for designing I2C master. For simulation Synopsys VCS compiler tool is used. Our interface design includes read and write operations and will be able to communicate to master and slave through the I2C. The verification environment has been developed and test cases have been implemented for I2C Design Under Test (DUT). The verification has been done using System Verilog Hardware Description and Verification Language.