Design of High Speed and Area Efficient FIR Filter Architecture using modified Adder and Multiplier

Finite impulse response (FIR) filter is one of the important components in any DSP and communication systems. Filter architecture contains many components; Two of the main components are adder and multiplier. Different types of adders and multipliers are available in the digital circuits, but need an efficient adder and multiplier design to design efficient filters. The existing adder is ripple carry adder and the existing multiplier is Wallace tree multiplier, both take more area and delay. To reduce the drawbacks in the existing system, the partial products generation and reduction needs a new efficient adder and multiplier named Reduced square root carry select (CSLA) adder and Bi-recoder multiplier respectively, is implemented. This modified adder and multiplier overcomes the existing drawbacks. It is implemented by verilog HDL. Then both adder and multiplier are compared with the existing adder and multiplier and the performance is analyzed. The design is implemented using Modelsim 6.3c and Xilinx ISE version 12.4. Finally the modified design is applied in the design of direct form FIR Filter and thus the efficient FIR Filter is obtained.