A Dynamic Scratchpad Memory Collaborated with Cache Memory for Transferring Data for Multi-bit Error Correction

Modern embedded processors include both scratchpad memory (SPM) and cache memory in their architectures. SPM's are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs). For correcting soft errors, we use Error Correcting Codes (ECC) like single-error correction double-error detection (SEC-DED) and SEC-DED double-adjacent error correction (SEC-DED-DAEC) and parity duplication approach. These approaches are used only error correction for less number of corrections and thus increases speed. This paper proposes a duplication scheme, cache-assisted duplicated SPM(CADS) to correct SEUs and SEMUs in data SPM lines detected by a low-cost error detecting code. This duplication approach does error detection in SPM which is faster than ECC providing multibit error correction. The extension is to include DMA with ring descriptors. The descriptor-based model provides the most flexibility in managing a system's DMA faster data transfers to or from Scratchpad memory. Asapu Harika | Mr. A. Sai Kumar Goud | Mr. Pradeep Kumar Reddy"A Dynamic Scratchpad Memory Collaborated with Cache Memory for Transferring Data for Multi-bit Error Correction" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14351.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14351/a-dynamic-scratchpad-memory-collaborated-with-cache-memory-for-transferring-data-for-multi-bit-error-correction/asapu-harika