Design and Implementation of CMOS 8 Bit Segmented Current-Steering DAC for High Speed Applications

The paper presents 8-bit segmented current steering DAC. The segmentation includes design of 4-bit Thermometer encoded DAC and 4-bit Binary weighted DAC. Register, thermometer encoder, current bias, current source are the sub blocks used in this design. Current sources are designed in the form of matrix architecture in thermometer encoded DAC, and inputs are controlled by using decoding logic. Current sources are designed in the parallel style in binary weighted DAC, and inputs are controlled by using binary numbers. Compared to other DAC types, the Current Steering DAC consumes minimum power hence used in higher speed applications. The design of 8-bit segmented CSDAC is done using 130nm technology consumes 80mW of power; peak to peak current is 824.06uV and supply voltage 1.2V.