An Efficient VLSI Implementation of Lossless ECG Encoder Design

An efficient VLSI implementation of a lossless electrocardiogram encoding circuit is designed for remote monitoring service. To reduce the wireless transmission power and the amount of storage data, an efficient lossless encoding algorithm had been built for the ECG signal compression. This algorithm consists of an adaptive predictor and a two-stage entropy encoder. The VLSI architecture of this work has the core area of 20308um2 and synthesized by a 180nm CMOS process. It can be operated at 100 MHz processing rate by consuming 1280uW. The data compression ratio is approximately 30.