Area efficient SR flip-flop designed using 90nm CMOS technology

In this paper SR flip-flop is designed to reduce area and power using 90nm technology for efficient utilization of the circuit. This is done using digital schematic (DSCH) and microwind application. Two designs have been proposed for SR flip-flop, namely fully automatic and semicustom design. In fully automatic design inbuilt active devices are used along with auto routing and placements. In semi-custom design inbuilt active devices are used with optimized manual routing and placement. The proposed schematic in case of fully automatic approach is designed by using DSCH and its equivalent layout is created using microwind. While in the case of semi-custom approach optimized layout is created with microwind. It can be observed from the simulated results that power is reduced by 81% and area consumption is improved by 15% in case of semi-custom design as compared to fully automatic design.