FPGA Implementation of High Speed Digital FIR Filter

Multipliers play an important role in today's digital world especially in DSP and DIP applications. With advances in technology, many researchers are trying to design multipliers which offer either of the following targets-high speed, low power consumption, regularity of layout and less area or even combination of them in one multiplier. Now-a-days researchers are focusing on low power and high speed. This may be possible by designing effective multiplies as these are involved in huge amount in almost all DSP architectures. To do so many multipliers are available such as Booth multiplier and Wallace tree multiplier. Booth multiplier gives high performance (accuracy) but with high delay, whereas Wallace tree multiplier gives high speed but with less accuracy.The proposed method of CSD multiplication has the ability to reduce truncation error, computation latency for constant word length multiplications. Furthermore Horner CSD multiplier with pipelining concept makes multiplier design power efficient and speed efficient. This novel CSD algorithm is used here to design a Digital FIR filter and the same is designed with the booth and Wallace tree algorithm and compared. It is observed that proposed design is better w.r.t no. of slices and delay in comparison with existing methods. This design is coded in Verilog HDL and targeted on the spartran-3 device of XILINX 14.5.