IMPLEMENTATION OF OPTIMIZED MULTIPLIER-ACCUMULATOR (MAC) UNIT WITH VEDIC MULTIPLIER AND FULL PIPELINED ACCUMULATOR: A REVIEW

As the technology is scaling down from micro scale to nano scale. At such scale a new field is evolved is called quantum computing. Quantum computation based on the principle of reversible operation, means the information is conversed and performs certain task in nanosecond. In order to implement a high speed multiplier a Vedic algorithm can be applied, because it perform simple operation and yield result quickly. The multiplication process involves two step generation of partial product and addition of partial product, these two steps are concurrently perform by the Urdhva Tiryakbhyam algorithm of Vedic Mathematics. The Multiplier and Accumulator (MAC) are the necessary elements of the digital signal processing for example filtering, convolution, and transformations. Power dissipation is recognized as a critical parameter in modern the objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. First, we introduce the concept of Vedic Multiplier. Then, we review existing methods to implement Vedic Multiplier for Accumulator design. We also discuss and analyze the advantages and disadvantages of these methods. Finally, we identify the potential challenges and future research directions in location prediction.