EXPLORATION ON POWER DELAY PRODUCT OF VARIOUS VLSI MULTIPLIER ARCHITECTURES

Multipliers plays a major role in signal processing and several other applications. High Performance VLSI architecture for multipliers is required in terms of low power dissipation, higer speed, lesser area. The most important consideration in Low power VLSI design is power dissipation. Researchers are taking more efforts to decrease the power consumption. The power dissipation efficiency can be identified by power delay product. The optimized design is one in which the architecture is having lesser power delay product. The methods used for doing multiplication are “add and shift” method. In parallel multipliers, the multiplier performance depends upon the partial products count. Array multiplier, On the fly conversion multiplier, vedic multiplier are designed and analysed. All the above multipliers are designed in Cadence Virtuoso Schematic Editor environment using 180nm technology. The power delay product for array multiplier, on the fly conversion multiplier, vedic multiplier is found to be be 5.41 pJ, 5.04 pJ, 4.58 pJ respectively . So out of three proposed multipliers Vedic multipliers shows better power delay product.