DESIGN OF LOW POWER AND DELAY SRAM MEMORY FOR SMART VEHICLES
Journal: International Journal of Mechanical Engineering and Technology(IJMET) (Vol.9, No. 4)Publication Date: 2018-12-27
Authors : SOMIL SHIVHARE; ANANIAH DURAI S;
Page : 335-345
Keywords : power dissipation; SRAM; T (transistor); bit lines; word lines; Sensitivity.;
Abstract
This paper focuses on the design of a 256 bit low power and low delay SRAM memory based on a proposed SRAM cell for smart vehicles. SRAM cell proposed in the paper consumes less power and low delay than 6T, 7T, 8T, 9T and 10T SRAM cell. This is featured by a parallel combination of PMOS and NMOS transistors connecting the ground. A least average power and delay is achieved among all mentioned SRAM cells for the proposed SRAM cell. Designs are implemented in tanner EDA using TSMC 130 nm technology.
Other Latest Articles
- WEB-BASED INCIDENTAL EMPLOYEE TRANSACTION SYSTEM (CASE STUDY: PT. MURAMOTO ELEKTRONIKA INDONESIA)
- A METHODOLOGY FOR SIMULATION AND VERIFICATION OF TOOL PATH DATA FOR 3-AXIS AND 5-AXIS CNC MACHINING
- DESIGN AND EVALUATION OF PERFORMANCE OF SOLAR AIR HEATER
- CULTURE AND SOCIAL ECONOMICAL SYSTEM OF SOUTHERN ARALBUYI DURING THE BRONZE AGE
- UTILIZATION OF BEND-TWIST COUPLING TO IMPROVE THE PERFORMANCE OF HYBRID MARINE COMPOSITE PROPELLER
Last modified: 2018-12-13 16:40:00