DESIGN OF LOW POWER AND DELAY SRAM MEMORY FOR SMART VEHICLES

This paper focuses on the design of a 256 bit low power and low delay SRAM memory based on a proposed SRAM cell for smart vehicles. SRAM cell proposed in the paper consumes less power and low delay than 6T, 7T, 8T, 9T and 10T SRAM cell. This is featured by a parallel combination of PMOS and NMOS transistors connecting the ground. A least average power and delay is achieved among all mentioned SRAM cells for the proposed SRAM cell. Designs are implemented in tanner EDA using TSMC 130 nm technology.