A Novel 128 bit adder using QCA

As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing this brief, we propose a new adder that outperforms all state-of-threat competitors and achieves the best area-delay tradeoff. The above advantages are obtained by using an overall area similar to the cheaper designs known in literature. In this we are reducing the delay which occurs in RCA and area which occurs in CLA. The 128-bit version reduced an area of 32.25?m2 and ADP of 542.