Design of Digital Finite Impulse Response Filter Using Different Low Power Mulitipliers
Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 6)Publication Date: 2014-06-30
Authors : M.Renuka; M.Nikhila; S.Dinesh Reddy;
Page : 632-646
Keywords : FIR FILTER; SPARTAN 3E; MAC; MULTIPLIER; LOW POWER; ADDERS;
Abstract
Filter. These methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to FIR filters to reduce power consumption and Distortion is also reduced. The proposed Finite Impulse Response (FIR) filter consists of delays, multipliers, adders. Multiplier consumes more power to reduce the power consuming designed multiplier using four different techniques. The multiplying operation is the basic operation in the FIR filter and is reduced by using these four techniques. In this project Finite Impulse Response (FIR) filter is design by 8-tap, I Implemented 8-tap to 12-tap filter and designed for different multipliers for 12-tap FIR filter, and also comparing powers of proposed FIR filter with implemented FIR filter. When the MAC operation is reduced in the filter automatically the power is also reduced. The proposed Finite Impulse Response (FIR) filter were synthesized and implemented using Xilinx ISE 9.2i on Spartan 3E and power is analyzed using Xilinx Power analyzer.
Other Latest Articles
- Secured and Verifiable Approach for Attribute Based Encryption in Cloud Computing
- Performance of a 3.3kV Resistive type Superconducting Fault Current Limiter
- Numerical Investigation for Cell Modeling Of Hydro Magnetic Axial Flow over a Cylinder
- A Review of Experimental study of Springback Determination of Ferrous Sheet Metals in an Air Bending
- Comparative Study: Garbage Collector in OODBMS
Last modified: 2014-07-04 22:18:48