FPGA Implementation of Digital PI Filter and Reset Loop Controller for DPLL

This paper presents implementation of Digital PI (Proportional- Integral) filter on FPGA and reset loop filter for Digital Phase Locked Loops (DPLL). The PI filter is derived from control theory, known as “proportional + integral” action. The proportional controllers are commonly used in industry and it takes control action based on the present control errors. The paper aims to obtain proper FPGA implementation results of Digital PI filter for DPLL and in addition to it, a reset loop filter is designed which involves, damping the filter response to improve the overall locking performance in DPLL. VHDL programming language is used for coding and the software used is Libero ide v9.1. The designed Digital PI filter and reset loop filter or controller in VHDL is verified with FPGA implementation results.