High Speed and Low Power FIR Filter Implementation Using Optimized Adder And Multiplier Based On Xilinx FPGA

T- Finite impulse response (FIR) filters are widely used in various DSP applications. The low-power or high speed techniques developed specifically for digital filters can be found in. Many applications in digital communication, speech processing (adaptive noise cancelation), seismic signal processing (noise elimination), and many other synthesis operations of signal require large order FIR filters ,since the number of multiply-accumulate (MAC) operations required per filter output increases linearly with the filter order, hence implementation of these filters of large orders is a challenging task. Here, we propose designing of FIR filter using high speed low-power multiplier adopting the new implementing approach. The multiplier we are using is Vedic Multiplier. It will reduce the number of partial products generated by a factor of 2. The carry save adder will avoid the unwanted addition and thus minimize the switching power dissipation. The architecture is designed in VHDL, simulate and synthesize in Modelsim and Xlinx ISE Software